The greatly increasing demand for memory space from application programs has led in the past to a rapid increase in the memory size of semiconductor memories. With an increasing memory size and the accompanying increased integration level in the fabrication of semiconductor memories, there is also an increase in the probability of memory cells of the data memory or semiconductor memory being fabricated defectively in the manufacturing process and thereby being non-functional. In order to avoid a high proportion of rejects in semiconductor memories, the semiconductor memories are fabricated with redundant memory areas. For this purpose, in the case of a semiconductor memory constructed from rows and columns, additional redundant rows and redundant columns are arranged on the memory chip.
Integrated circuits, in particular integrated semiconductor memories, are subjected to a test method after fabrication in order to test the logical and dynamic behaviour of the circuit and at the same time on the one hand to detect defective circuits and on the other hand to check the performance of the circuit by evaluating the test results. In known test methods, an automatic test machine is used to generate test patterns that are applied to the integrated circuit. At the outputs of the integrated circuit, the response patterns are read out by the automatic test machine and compared with desired response patterns. The integrated circuit is defect-free when the output response patterns correspond to the desired response patterns. The integrated semiconductor memories are often constructed with BIST structures (Built-In Self-Test). These BIST structures have built-in self-test units. This means that additional logic circuitry that has test pattern generators and evaluation units for the test patterns is integrated in the integrated semiconductor memory. In embodiments of this type, the automatic test machine supplies only one clock signal for the circuit to be tested and, on the basis of the data read out by the evaluation units for the test patterns, determines whether a defective or defect-free semiconductor memory is present. Integrated circuits with self-test units generally have memory units or memory registers that afford the possibility of generating test patterns (for example BILBO registers (Built-In Logic Block Observation), which generally have four operating states). Counters are generally employed in order to test all the addresses in a defined order. Furthermore, a small number of test patterns are defined, which test patterns are generally stored. The abovementioned explanations relate to a logic test.
A redundancy control logic integrated in the semiconductor memory controls the access to the redundancy address memory and to the redundancy data memory. The redundancy address memory has address memories in which the faulty addresses of the defective memory cells of the memory cell array of the main data memory are stored. Since the faulty addresses stored in the address memories are lost in the event of failure of the power supply, these faulty addresses detected during the testing of the semiconductor memory are additionally permanently programmed into a read-only memory. These addresses programmed into the read-only memory can be written to the redundancy address memory again from the read-only memory, as required.
If a defective memory cell or data memory unit in the memory cell array of the main data memory is identified in a test run, the error address of the defective memory cell is written to an address memory unit or an address memory register of the redundancy address memory. In the case of an access to this error address, the assigned memory cell within the redundancy data memory is accessed rather than the defective memory cell within the main data memory. On account of this readdressing, it is possible to a certain degree (depending on the number of defective memory cells and the size of the redundancy data memory) to replace defective memory cells within the main data memory by redundant memory cells in the memory cell array of the redundancy data memory.
Various embodiments of test methods are known. DE 39 24 695 A1 discloses an internal self-test and redundancy programming method for memory circuits. When an operating voltage is switched on by an internal self-test processor with a microprocessor, the memory circuit is tested and the error addresses are determined. The error addresses determined are compressed and stored in a register bank of the self-test processor. From the distribution of the error addresses, the redundancy structure is determined and the corresponding redundancy bit lines and redundancy word lines are activated. Thus, in this method, firstly the entire number of error addresses of the entire memory is determined and only afterward does the calculation of the redundancy strategy begin. This means that a very large volume of data has to be stored since, by means of error-detecting codes, the positions of the defective memory cells are determined and a complete bitmap of all the defective bits is created and stored. One disadvantage of such test methods and circuit arrangements is that this two-stage nature of the test procedure means that a great deal of time is required for testing and repairing and a highly cost-intensive method also results from this. Furthermore, very large memory units are required for the volume of data of the very large bitmaps. A further disadvantage results from the fact that only entire word and/or bit lines can be replaced by means of this method. By way of example, if only one memory cell is defective in a row with 256 memory cells, then the complete row is replaced and 255 defect-free memory cells are wasted. This results in a considerable waste of space in the available area of the semiconductor memory, which has to be made appropriately large in the case of test and repair methods of this type.
Furthermore, the published German Patent Application DE 101 10 469 A1 discloses a test and repair method and also an integrated memory. The method can be used to repair integrated memories that have already left the test phase with the manufacturer and are in use in current operation. If a defective row or column is identified by a self-test unit in current operation, the self-test unit generates an error signal for this row or column and generates a repair signal depending on a comparison of the error signal with an average error signal. As a result of the triggering of the repair signal, a self-repair unit, in current operation, replaces the defective row or column by a redundant row or redundant column. The test method also enables single-cell defects to be detected and repaired by means of an entire row or an entire column. One disadvantage is that, by virtue of the error-detecting and error-correcting codes, in addition to the redundant rows and redundant columns, further memory cells are lost as useful information and, moreover, a repair is possible only by means of redundant rows and/or redundant columns. Consequently, here, too, a very high number of defect-free memory cells are wasted and an ineffective and inefficient repair strategy is taken as a basis.
Furthermore, the published German Patent Application DE 100 02 127 A1 discloses a test method and a data memory in which, during the test procedure, an address of a memory cell of a main data memory that has been identified as defective is immediately readdressed to an assigned redundancy memory unit within a redundancy data memory. The error detection and the readdressing of each individual address are therefore effective directly successively during the test run rather than only after all the faulty addresses have been detected. One disadvantage of this method and this arrangement is that, on account of the limited size of the redundancy memory unit, only a relatively small number of defective memory units can be replaced by redundant memory units. Therefore the result is that there are many rejects of main memories or data memories that cannot be completely repaired, or, on the other hand, the redundancy data memory has to be very large in order to be able to repair a highest possible number of defective memory cells by redundant memory cells.
The known method is not based on a specific test strategy in order to optimize the identification of the defects or to be able to detect specific categories of defects more simply. The column-oriented defect, in particular, is a major problem in the case of this method. A further disadvantage here is that the defective data memory units are immediately repaired individually, as a result of which an effective repair in comparison with methods in which firstly a plurality of defects are detected and only then is a repair strategy determined is generally possible only to a very limited extent. Furthermore, no redundant rows and/or redundant columns are made available for the repair.